Conventionally, a current-source power converting apparatus that generates drive signals of switching elements based on current references is known. For example, there is known a current-source power converting apparatus that generates a drive signal of a switching element by using logical AND of one PWM pulse signal and a NOT signal of another PWM pulse signal among PWM pulse signals of three different interphases generated by comparing current references (hereinafter, described as line-to-line current references) corresponding to three different interphases (UW-phase, VU-phase, and WV-phase) and a carrier signal (for example, triangle wave signal) (for example, see Japanese Patent Laid-open Publication No. H09-182458).
In a current-source power converting apparatus that outputs power of a DC source via switching elements, when all of the switching elements are turned off in a state where a carrier signal is larger or smaller than all of three line-to-line current references, current from the DC source is interrupted. Because the DC source has a large inductance, interruption of current from the DC source causes generation of overvoltage.
Therefore, in the conventional current-source power converting apparatus, when the carrier signal is larger or smaller than all of the three line-to-line current references, a current vector, whose magnitude is zero, is output to ensure a current path of the DC source. Specifically, the current-source power converting apparatus described in Japanese Patent Laid-open Publication No. H09-182458 is provided with a circuit, which monitors a state in which the carrier signal is larger or smaller than all of the three line-to-line current references, and a D flip-flop circuit which, in such a state, generates drive signals for driving switching elements on both pole sides, i.e., positive and negative sides, of a predetermined phase (for example, U-phase) for outputting a current vector whose magnitude is zero.
However, in the above conventional current-source power converting apparatus, propagation delay occurs by propagation of PWM pulse signals generated by comparing the line-to-line current references and the carrier signal and a signal indicating whether the carrier signal is rising or falling through a D flip-flop circuit. Therefore, in logic circuits after the D flip-flop circuit, a pulse (glitch) having a pulse width of a propagation delay time difference t, which is not normally generated and has a relatively short width, is generated and distortion of an output current occurs due to this.